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EOSL_EDA Design Intern (S100/S200) at ITRI

, , -

Full Time

Start Date

Immediate

Expiry Date

06 May, 26

Salary

0.0

Posted On

05 Feb, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

AI-Driven EDA, Chip Layout Optimization, Numerical Analysis, SoC Verification, IP Verification, Parameter Exploration, Optimization Algorithms, 3D Chip Layout, Power Performance Area, Generative Programming

Industry

Research Services

Description

This internship is in ITRI's Electronics and Optoelectronics Systems Research Laboratories (EOSL). Intern will work on the following topics / tasks: AI-Driven EDA Development and Research Develop fully automated parameter exploration and optimization algorithms and tools based on existing EDA platforms. Design and implement 2.5D/3D chip layout algorithms with considerations for power, performance, and area (PPA). Develop next-generation numerical analysis and computational solvers to accelerate convergence speed. Develop generative programming–based IP and SoC verification technologies to improve verification efficiency and convergence. Qualifications: Major and student level: Master's or Ph.D. degree. Required/desired background with specific skills (software, equipment, processes, etc.): Educational or research background relevant to AI-driven EDA, chip layout optimization, numerical analysis, or SoC/IP verification. Language or other qualifications: Must be able to work on-site at the Hsinchu Zhongxing Campus.

Responsibilities

The intern will work on AI-driven EDA development and research, focusing on automated parameter exploration and optimization algorithms. They will also design and implement chip layout algorithms and develop numerical analysis and computational solvers.