At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a ground-breaking and uncommonly dedicated Physical Design Engineer in Munich. As a member of our multifaceted group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple’s customers every single day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, timing & logic design teams, with a critical impact on delivering best in class PHY designs. You will be required to do physical designs of best in class PHY design. Join us!

DESCRIPTION

Responsibilities include especially, but are not limited to: Static timing analysis for high speed IP’s, incl. analog mixed signal interfaces. CTS setup and optimisation for high frequency, multiple clocks networks. Developing floor-plans under strong area constraints with best aligned for full chip integration. Account and optimise for low power during every implementation step. Perform full place and route flow on hierarchical design blocks and meet all design targets for timing, area and power on a challenging project timeline. Implement functional, timing, noise, EMIR, etc. ECOs. Run all types of physical design verification give feedback to hard macro owners and other involved teams and perform design reviews. - Participate in physical design methodologies meetings - Assist in our AMS flow development to improve our best in class env. even further.

MINIMUM QUALIFICATIONS

• Knowledge hand on experience Floor-planning and Place & Route, Physical verification, timing closure, power/functional verification.
• Ability to fluently speak and write in English.

PREFERRED QUALIFICATIONS

• BSc in Electrical Engineering or equivalent.
• The ideal candidate will have experience on high PHY and/or SOC designs.
• Experience in low power implementation for both static and dynamic, knowledge on UPF power intent flow.
• Deep Understanding of timing constraints, timing exceptions, clock setup, timing debugging.
• Proven Knowledge of Basic SoC Architecture and HDL languages like Verilog.
• Power user of industry standard Physical Design, Static Timing Analysis and Synthesis tools.
• Deep Understanding of scripting languages such as Perl/TCL/Shell.
• Hands on experience on functional ECO implementation and equivalence checking and debugging.
• Deep Understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
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Please refer the Job description for details