Experienced ASIC Design Engineer at Sandisk

Omer, South District, Israel -

Full Time

Start Date

Immediate

Expiry Date

09 Jun, 26

Salary

0.0

Posted On

11 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design, RTL Implementation, SystemVerilog, Micro-architecture Definition, IP Integration, SoC, Design Specifications, Verification, Physical Design, LINT, CDC, Power Estimation, Functional Coverage, Code Coverage, Security Features, SSD Controllers

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description We are seeking a highly skilled Senior ASIC Design Engineer to take technical ownership of advanced IP subsystems and contribute to the development of best‑in‑class, complex, high‑performance designs used in world‑leading products Sandisk offers. The ideal candidate will demonstrate proven experience in ASIC design from micro‑architecture definition through RTL implementation and validation - and work across multiple teams to ensure successful IP integration and deployment. This role operates in a fast‑paced, dynamic environment, requiring adaptability and strong communication skills. The engineer will also collaborate closely with engineering teams overseas, driving alignment and ensuring seamless end‑to‑end execution across global development sites. Key Responsibilities: Take full ownership of the definition, ASIC design, and development of major blocks or subsystems within complex IPs for next-generation SoCs. Define micro-architecture and author detailed design specifications aligned with architectural goals and performance targets. Implement high-quality, efficient RTL designs (in SystemVerilog), ensuring functionality, performance, and power goals are met. Collaborate closely with architecture, verification, physical design, product, and SoC integration teams to deliver top-tier IP solutions. Drive debug, coverage closure, and continuous quality improvement throughout the development lifecycle. Actively contribute to the core technology team’s growth by sharing technical expertise, mentoring peers, and driving innovation in ASIC design methodologies and tools. Participate in design and code reviews, providing constructive feedback and ensuring design best practices are followed. Qualifications BSc/MSc in Electrical Engineering. Previous experience of at least 7 years as an ASIC Design Engineer with a strong focus on security features for SSD controllers. Hands-on Knowledge in Verilog / System Verilog on complex blocks Self-motivated and self-directed, however, must have demonstrated the ability to work well with people A proven desire to work as a team member, both on the same team and outside of the team Ability to troubleshoot and analyze complex problems. Excellent analytical and problem-solving skills with a focus on performance optimization. Excellent communication (written and verbal) and interpersonal skills. Hands-on Knowledge in LINT, CDC, and Power Estimation tools Hands-on knowledge of functional coverage definitions and code coverage understanding Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Omer Office--LOC_SNDK_Omer Office

Responsibilities

The engineer will take full ownership of defining, designing, and developing major blocks or subsystems within complex IPs for next-generation SoCs, implementing high-quality RTL designs in SystemVerilog to meet performance and power goals. Responsibilities also include collaborating with various teams, driving debug and quality improvement, and mentoring peers on ASIC design methodologies.