Experienced ASIC Verification Engineer at Sandisk

Omer, South District, Israel -

Full Time

Start Date

Immediate

Expiry Date

09 Jun, 26

Salary

0.0

Posted On

11 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

UVM Methodology, System Verilog, Verilog, RTL Development, ASIC Verification, Debugging, Analytical Skills, Communication

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description The ASIC Group, is part of worldwide organization responsible of delivering custom ASIC for NAND based storage application like SSD, USB, SD for various markets such as consumer, automotive and enterprise. The group has all of the ASIC functions internally and working in a full COT mode. The ASIC-IP design and verification group is responsible for definition, design, verification, and support for all complex IP that build each SOC done on Sandisk for all segments. Strategic IPs are developed to all areas from retail, iNAND (cell phones and client solution) through Client SSD solution and Enterprise SSD. As part of the team, you will be part of the global effort to: Define, design, verify, and document RTL development in Verilog/System Verilog of complex world wide strategic IPs Interact closely with architecture teams and all SOC teams in Sandisk Work and develop under world class ASIC methodology development stages Significant contribution to design and verification and methodology on making complex IPs and flows Become a significant person in a vast growing team Qualifications BSc in Electrical Engineering At least 10 years of experience in ASIC Verification with UVM Methodology and System Verilog Excellent analytical and debugging skills A good eye for details Advanced verbal and written communication skills Collaborates to develop self and others within group Strong professional leading skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: ASIC Development Engineering Work Location: Omer Office--LOC_SNDK_Omer Office

Responsibilities

The role involves defining, designing, verifying, and documenting RTL development in Verilog/System Verilog for complex, world-wide strategic Intellectual Properties (IPs). Responsibilities also include interacting closely with architecture teams and contributing significantly to design, verification, and methodology for complex IPs and flows.