Fabric R&D Engineer at Advanced Micro Devices
San Jose, CA 95124, USA -
Full Time


Start Date

Immediate

Expiry Date

23 Oct, 25

Salary

286560.0

Posted On

23 Jul, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Design, Communication Skills, Structures, Manufacturing

Industry

Electrical/Electronic Manufacturing

Description

PREFERRED EXPERIENCE:

  • Programmable logic fundamentals
  • Next generation process and packaging technologies
  • Binning and circuit margins, including VID, Aging
  • Regulators, SRAM design, LUTs, NOCs, Clocking
  • Circuit techniques for high performance and low power operations
  • Industrial and automotive FUSA requirements
  • Design for Manufacturing and Design for Debug
  • Micro-architecture of dense, repeating structures
  • Strong written and verbal communication skills
Responsibilities

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_

THE ROLE:

As a senior design engineer in our FPD BRICS team, you will be responsible for leading and optimizing the Fabric PPC in the Adaptive & Embedded Computing Group (AECG). You will be driving new ideas and capabilities in the programmable fabric in current and future products. You will be leading the evaluation of future architectures by closing working with Architecture and Manufacturing teams. You will enable test chip designs and provide technical direction for skilled design engineers to help evaluate and realize key IP and technologies. You will be reviewing IP designs for quality, performance, power, and cost. Additionally, you will interact with the various Silicon development teams including digital and analog circuit designers, custom layout designers, physical designers, integration teams, and sign-off teams.

Loading...