FE Design and Timing Analysis Engineer

at  Apple

SUMMARY

Posted: Oct 29, 2024
Role Number:200576053
Come and join Apple’s growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply.

DESCRIPTION

As a Front End and Timing Analysis Engineer, you will be involved with all phases of implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. Your responsibilities include, but are not limited to: • Generate chip or block level static timing constraints. • Synthesize design with UPF/DFT/BIST. • Close timing on critical blocks by working with design and PD teams. • Perform timing optimization and implement the design for functionality. • Generate and implement functional ECOs. • Run static timing analysis flows at chip/block level and provide guidelines to fix violations to other designers. • Participate in establishing/improving CAD and design flow methodologies. • Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating proper checks at every stage of the design process.

MINIMUM QUALIFICATIONS

• Bachelors and 10+ years of relevant industry experience.
• Knowledge of the ASIC design flow, synthesis, static timing analysis, RTL to Post Synthesis netlist.
• Exposure to industry standard Timing, Logic Equivalence, Physical Design and Synthesis tools.
• Proficient in scripting in TCL, Perl or Python.
• Knowledge of basic SoC Architecture and HDL languages like Verilog / System Verilog to collaborate with our logic design team for timing fixes and functional ECOs.

PREFERRED QUALIFICATIONS

• Hands-on experience in timing/SDC constraints generation, analysis, and management.
• Knowledge of timing corners, operating conditions, process variations, and signal integrity-related issues.
• Knowledge of Place and Route steps including floor planning, CTS, Routing and timing ECOs.
• Understanding of UPF and low-power design and implementation techniques.
• Understanding of DFT methodologies including Scan and BIST.

Please refer the Job description for details