Start Date
Immediate
Expiry Date
13 Jan, 26
Salary
0.0
Posted On
15 Oct, 25
Experience
2 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
ASIC Design Flow, Synthesis, Static Timing Analysis, RTL, Post Synthesis Netlist, TCL, Perl, Python, Timing Constraints, Timing Optimization, Low Power Design, SoC Architecture, Verilog, Functional ECOs, Signal Integrity, Physical Design
Industry
Computers and Electronics Manufacturing