FE STA engineer at Apple

Herzliya, Tel-Aviv District, Israel -

Full Time

Start Date

Immediate

Expiry Date

26 Aug, 26

Salary

0.0

Posted On

28 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, ASIC Design, Timing Sign-off, Primetime, SDC Constraints, Tcl, Perl, Synthesis, DFT, Backend Methodology, SoC Design, Timing Closure

Industry

Computers and Electronics Manufacturing

Description

As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis. DESCRIPTION Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. MINIMUM QUALIFICATIONS 5+ years of work experience Knowledge of the ASIC design timing closure flow and methodology At least 2+ years of experience in writing ASIC timing constraints and timing closure Expertise in STA tools (Primetime) and flow Knowledge of Timing corners/ modes Hands on experience in Timing / SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools PREFERRED QUALIFICATIONS B.Sc / M.Sc in Electrical or Computer Engineering

Responsibilities

Responsible for SoC timing sign-off, including the development of STA flows and ownership of timing constraints from synthesis to sign-off. Collaborates with RTL, CAD, and Physical Design teams to ensure timing closure and verify design intent.