PREFERRED EXPERIENCE:

• C++ programming and scripting language capabilities
• Computer architecture background with industry experience in architecting processors, caches, and interconnect.
• Familiarity with Digital RTL Design, Software Development, Verilog HDL. Experience writing and debugging RTL.
• Experience collaborating effectively towards the success of a project by working closely with a diverse team across disciplines.

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

AMD’s Cores Organization delivers industry leading CPU’s and caches that are the foundation of AMD’s server, client, and gaming business. We are looking for a Fellow-level experienced design engineer to join this innovative team as a technical expert and work in the areas of performance modeling, performance analysis, and microarchitecture development. The candidate will be a key contributor and leader for AMD’s next generation cores and caches. The candidate will join the team based in Fort Collins, CO.

KEY RESPONSIBILITIES:

• Collaborate with a small, dedicated team of hardware and software engineers to optimize the performance of CPUs, caches, and interconnect.
• Develop and enhance cycle-accurate core, cache, and SoC (System on a chip) performance simulators.
• Develop other simulators at different abstraction levels.
• Use those simulators as well as analytical methods, emulation, and post-silicon observation and experimentation to develop and evaluate microarchitecture improvements.
• Develop and improve tools and methodology for performance analysis of workloads.
• Guide and mentor junior engineers.