Formal Validation Engineer at Apple

Cupertino, California, United States -

Full Time

Start Date

Immediate

Expiry Date

27 May, 26

Salary

190900.0

Posted On

27 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Formal Verification, Design Blocks, IP Verification, Micro-architecture Specification, Formal Verification Test Plans, Property Proving, Digital Logic Design, Computer Architecture, Formal Models Development, Verification Code Base, Correct-by-Construction Methodologies, Verilog, System Verilog, Algorithm Design, Scripting Language, C++

Industry

Computers and Electronics Manufacturing

Description

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do. DESCRIPTION APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image processing IP, Neural Networks IP, Memory/DMA controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.); Work with Apple Silicon's world-class SOC and IP design engineers to develop a formal micro-architecture specification; Develop comprehensive formal verification test plans; Help improve micro-architecture by proving properties, finding bugs and performing digital logic design and computer architecture; Craft novel and creative solutions for verifying complex design micro-architectures; Develop and implement re-usable and optimized formal models and verification code base; Architect correct-by-construction design methodologies for improved formal verification efficiency and productivity. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $127,234 - $190,900/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. MINIMUM QUALIFICATIONS Bachelor’s degree or foreign equivalent in Electrical Engineering or related field. Experience and/or education must include: Utilizing design and verification techniques, tools, and methodologies to verify and improve chip design and architecture. Designing and implementing verification environments using verilog or system verilog. Utilizing algorithm design to verify complex designs. Knowledge or experience architecting correct-by-construction design methodologies for improved verification efficiency. Utilizing scripting language skills to develop and maintain verification infrastructure. Leveraging programming language skills such as C, C++ and Matlab to verify complex data path designs. Utilizing ASIC, computer design and microprocessor knowledge to drive and maintain deliverables and support cross-functional engineering. Leveraging design knowledge to drive design teams and improve SoC architecture. Utilizing digital system design and computer knowledge to debug RTL to achieve the performance and functional goals of the design. PREFERRED QUALIFICATIONS N/A

Responsibilities

The engineer will conduct complete formal verification for various design blocks and IPs, such as CPU, Cellular, and Neural Networks, while collaborating with design engineers to develop formal micro-architecture specifications. Responsibilities also include developing comprehensive test plans, improving micro-architecture by proving properties, finding bugs, and crafting creative solutions for complex designs.