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Formal Verification Engineer at Apple
, , Israel -
Full Time

Start Date

Immediate

Expiry Date

18 Apr, 26

Salary

0.0

Posted On

18 Jan, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Mathematics, CS Theory, Model Checking, RTL, Verilog, Analytical Thinking, Motivation

Industry

Computers and Electronics Manufacturing

Description
Ready for an intellectual challenge that combines Mathematics and CS theory in the context of hardware development? Keep reading. In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence Not in the Formal domain? No worries, we offer thorough training to learn the theory and practice directly from our team experts DESCRIPTION In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence . The position is relevant for both Herzliya/ Haifa site MINIMUM QUALIFICATIONS Excellent graduates from leading universities Analytical thinking Highly motivated PREFERRED QUALIFICATIONS BS.c / MS.c in CS & Mathematics
Responsibilities
You will be responsible for developing mathematical proofs using model checking tools to find RTL (Verilog) bugs or prove their absence. The position is relevant for both Herzliya and Haifa sites.