Formal Verification Engineer at Apple

Cupertino, California, United States -

Full Time

Start Date

Immediate

Expiry Date

15 Jan, 26

Salary

0.0

Posted On

17 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Formal Verification, Silicon Validation, Digital Logic Design, Verification Techniques, Security Requirements, Micro-Architecture, Formal Models, Scripting Languages, Debugging Skills, Interpersonal Skills, CPU Design, GPU Design, Cellular Designs, Temporal Logic, EDA Tools, Cache Coherence

Industry

Computers and Electronics Manufacturing

Description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. Learn from the best Formal Verification team in the world and acquire experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design. Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly. DESCRIPTION As a formal verification engineer working the complete formal verification for single or multiple design blocks and IP’s (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: - Working with Apple Silicon's world-class Security Enclave design engineers to develop a formal micro-architecture specification - Developing comprehensive formal verification test plan that includes unique security requirement verification - Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. - Crafting novel and creative solutions for modelling security attacks and proving robustness of complex design micro-architectures - Developing and implementing re-usable and optimized formal models and verification code base - Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity. MINIMUM QUALIFICATIONS A minimum of a bachelor's degree and a minimum of 3 years of relevant industry experience in silicon validation software engineering or related field. PREFERRED QUALIFICATIONS Hands on experience with VLSI and digital logic design and verification techniques or formal methods and their application to hardware, software, or systems Interest in learning and becoming an expert in SoC, CPU, GPU, or Cellular designs. Detail oriented approach and desire to overcome challenges is required. Formal Method or Formal Verification technologies knowledge is a plus. Knowledge and experience in interpreting hardware specifications. Temporal logic assertion-based languages such as SVA or PSL. Experience in using EDA formal tools and tool development experience is plus. Proficiency in any scripting language with excellent debugging skills. Excellent interpersonal skills. Passionate about developing world-class/innovative formal verification solutions. Exposure to CPU instruction-set architectures, memory consistency or cache coherence principles

Responsibilities

As a formal verification engineer, you will work on the complete formal verification for various design blocks and IPs. You will collaborate with design teams to prove properties of the design, find bugs, and improve micro-architecture.