Formal Verification Engineer (4 positions) - Hybrid in Sunnyvale, CA
Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, or equivalent practical experience.
5+ years of hands-on experience in Formal Verification.
In-depth experience with formal verification techniques such as datapath verification, sequential equivalence checking, X-propagation analysis, clock gating, and connectivity validation.
Strong grasp of complexity reduction and abstraction strategies in Formal Verification.
Demonstrated analytical problem-solving skills, particularly in addressing complex design challenges.
Proven ability to work collaboratively with cross-functional teams including architecture, design, and verification.
Proficiency in hardware description and assertion languages (SystemVerilog, SVA).
Solid scripting skills using Python, Perl, or Tcl.
Hands-on experience with leading formal verification tools such as Cadence JasperGold or Synopsys VC Formal.

SUMMARY

As a Formal Verification Engineer, you will be instrumental in ensuring the reliability and correctness of complex systems through rigorous verification processes. Reporting to the lead engineer, your role will leverage core skills in Python, SystemVerilog, and electrical engineering to develop and implement verification methodologies. Your premium expertise in FPGA and root cause analysis will enhance project outcomes, while your analytical skills will drive effective problem-solving. Join our innovative team to contribute to cutting-edge technology solutions and uphold the highest standards of system integrity.
Job Type: Contract
Pay: $50.00 - $60.00 per hour
Work Location: In perso

Please refer the Job description for details