FPGA Design Engineer at Arista Networks

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

21 May, 26

Salary

170000.0

Posted On

20 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verilog, System Verilog, FPGA Design, Control Path Design, Ethernet, AXI, Scripting, Timing Analysis, Debugging, Simulation, Collaboration, Hardware Specifications, Resource Constraints, State Machines, Chip IO Interfaces, Functional Verification

Industry

Computer Networking Products

Description

Company Description Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description Who You’ll Work With As a core member of the FPGA Design and Verification team, the candidate will be part of a fast-paced, high caliber team Designing and Verifying control path FPGA's for Arista Network products used in the computer networking industry's largest data centers. The FPGA Design Engineer is responsible for all aspects of the control path FPGA, from collecting the functional requirements that are needed, to reviewing the schematics of the board design engineer, to verifying the design using the latest tools, to bring-up and support of such a vital part of the networking hardware design. The successful candidate will work closely on a project from its early conception to the customer shipment and support when needed. They will work with fellow engineers and members of the hardware, software, and manufacturing team to understand the feature requirements, design and validate it. Besides closely working with the hardware engineers in designing the board, they will also review the hardware specifications and take ownership of the control path FPGA. What You’ll Do Verilog/System Verilog code development, integration, simulation, and testbench creation Perform FPGA implementation including synthesis, place and route, timing analysis, and debug Collaborate with hardware and software engineers for rapid system-level bringup and debugging of network switch designs Participate in fpga level code reviews, as well as schematic and board design reviews Incorporate scripting to process input/output data for FPGA toolchains Concepts and Skills You May Learn Data and control architectures of a modern ethernet switch, including chip IO interfaces such as Interlaken, Ethernet PHY/MAC, PCIe, SMBus, SPI, MDIO, JTAG, etc. Protocols using Ethernet, such as PTP, SFlow, POE, etc. Real world applications and the challenges of FPGA design, including resource/timing constraints, race conditions, state machines, etc. Exposure to multiple FPGA vendor architectures, IDEs, and toolchains (Xilinx, Altera, Microsemi, etc.) Simulation software for FPGA functional verification How to read and interpret PCB schematics as they pertain to FPGA code development Cross-functional collaboration to ideate and solve system-level technical challenges Qualifications 1-5 years of designing Verilog/System-Verilog RTL code Control path design experience (Ethernet Data path design experience preferred) On-chip bus interfacing design experience e.g. AXI (Streaming bus interfacing design experience preferred) FPGA design resource and timing closure experience preferred Python/TCL/Scripting experience Compensation Information The new hire base pay for this role has a pay range of $110,000 to $170,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location. #LI-SP1 Additional Information Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.

Responsibilities

The FPGA Design Engineer will design and verify control path FPGAs for Arista Network products. They will collaborate with hardware, software, and manufacturing teams throughout the project lifecycle.