Who You Are

• A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes.
• Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets.
• Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room.

What We Need

• BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout.
• Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).
• Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC)).
• Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).

What You Will Learn

• How RISC-V CPU and AI accelerator IP is hardened and delivered to external licensees on the most advanced process nodes.
• Multi-variant IP delivery: porting the same block across nodes, foundries, and PPA targets.
• Direct impact on IP deal timelines, since your PPA and schedule data feeds our customer commitments.
• Front-to-back co-design with architecture, RTL, and chiplet integration teams.