Our company is developing a cutting-edge wireless communication system to connect multiple portable devices. Long range, high data rates, low latency, resistance to interferences, and multipath make this problem particularly challenging, giving the candidate unique opportunities to research, design, and implement the next-generation radio communication systems.
We are looking for an experienced and driven FPGA Design Engineer to join our team. In this role, you will be responsible for the design, integration, and implementation of RTL modules based on system requirements. You’ll collaborate closely with verification engineers and system architects, contributing across the full design cycle - from IP integration to timing closure and deployment.

REQUIREMENTS

• 5+ years of experience in FPGA or VLSI (FrontEnd) design.
• Strong Verilog/SystemVerilog skills (SystemVerilog preferred).
• Intermediate-level proficiency in C/C++.
• Experience with lint-clean RTL development and structured code practices.
• Solid understanding of SDC constraints and static timing analysis.
• Familiarity with clock domain crossing (CDC), reset domain crossing (RDC), and low-power design methodologies.
• Experience with wireless communication technologies and signal processing concepts, such as MIMO and OFDM.
• Awareness of verification concepts and methodologies, including UVM.
• Experience implementing fixed-point DSP algorithms in RTL is a strong plus.

REQUIRED SKILLS AND ABILITIES:

• Strong analytical and problem-solving mindset with a detail-oriented approach.
• Effective communication skills and the ability to work across multidisciplinary teams.
• Willingness to learn and adapt to new challenges and evolving technologies.
• Commitment to quality, innovation, and high-performance design.

• Implement lint-clean RTL modules based on architectural requirements and C/C++ descriptions.
• Integrate third-party IP blocks into the FPGA design and ensure smooth functionality.
• Contribute to verification by adding sequences/tests to existing UVM environments and assisting with coverage closure.
• Analyze code coverage and address any gaps to ensure complete functional validation.
• Generate and manage SDC constraints for assigned modules.
• Debug and resolve module-level timing violations during STA analysis.
• Deliver stable, production-ready modules for system-level integration.