JOIN OUR TEAM AT AN EXCITING TIME OF GROWTH!

Cerio is a pioneer reshaping the future of accelerated computing. Our commitment to delivering superior customer experiences and economically sustainable solutions sets us apart in the industry.
This is an exciting opportunity for an FPGA Designer, at the intermediate or senior level, who would also like to develop their skills in a DevOps position. We will enable you to be involved in making dramatic changes to the compute and Data Center industry by making a significant contribution to our disruptive next generation solutions for Composable Disaggregated Infrastructure (CDI). Built on the foundation of a supercomputing underlay fabric, the Cerio platform provides standards-based, low-code composability services for the cost-effective and efficient management of AI/ML infrastructure.

BONUS IF YOU HAVE KNOWLEDGE AND EXPSOURE OF

• Intel FPGA design flow and tools
• AMD/Xilinx FPGA design flow and tools
• Protocols related to highspeed, low latency, and switching data path
• ASIC/FPGA verification methodologies such as UVM
• System Verilog
• Low power design techniques, for ASIC/FPGA
• Design optimization for speed/timing, power, area

The experience you bring

• A minimum of 6 years experience as an ASIC/FPGA Designer
• A degree in Electrical Engineering or a related field
• Solid experience in Altera/Quartus FPGA build and release process
• Expertise in operating Linux environment with good command over any scripting language such as Shell, Python, etc.
• Deep experience with Altera/Intel and Cadence EDA tools
• Experience with simulation, synthesis, timing closure and backend FPGA/ASIC tool flow
• Strong hands-on knowledge of Python, Bash, Jenkins, GitHub CI/CD pipeline tools
• Strong troubleshooting and triaging capabilities, passionate to learn & quickly adapt to the new technology, process knowledge

• Develop your skills with Placement, Timing Closure & New Part/Board Setup in Intel Quartus and Agilex based devices
• Work with Hardware design to define and capture the FPGA configuration requirements
• As time permits, be involved in the Design of RTL code for product inclusion
• Develop and maintain Continuous Integration processes for FPGA/ASIC build flows & applications by accessing and using tools like Jenkins, GitHub etc.
• Troubleshoot and triage on the build pipeline, infrastructure and tools issues
• Execute medium to large tasks independently & provide regular updates to stakeholders
• Develop mock-ups or requirement prototypes for features of moderate to high complexity and effectively articulate the requirements to relevant stakeholders

The experience you bring

• A minimum of 6 years experience as an ASIC/FPGA Designer
• A degree in Electrical Engineering or a related field
• Solid experience in Altera/Quartus FPGA build and release process
• Expertise in operating Linux environment with good command over any scripting language such as Shell, Python, etc.
• Deep experience with Altera/Intel and Cadence EDA tools
• Experience with simulation, synthesis, timing closure and backend FPGA/ASIC tool flow
• Strong hands-on knowledge of Python, Bash, Jenkins, GitHub CI/CD pipeline tools
• Strong troubleshooting and triaging capabilities, passionate to learn & quickly adapt to the new technology, process knowledge.