FPGA/SoC Engineer for NATO at WLG

La Spezia, Liguria, Italy -

Full Time

Start Date

Immediate

Expiry Date

25 Mar, 26

Salary

0.0

Posted On

25 Dec, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

FPGA Design, SoC Architectures, HDL, Verilog, VHDL, Linux Kernel Programming, Agile, Scrum, Git, Continuous Integration, Test-Driven Development, Secure Coding Practices, Debugging, Analytical Skills, Documentation, Collaboration Tools

Industry

Financial Services

Description

Would you like to join the leading international intergovernmental organization? The Centre for Maritime Research and Experimentation (CMRE) is an established, world-class scientific research and experimentation facility that organizes and conducts scientific research and technology development centred on the maritime domain. It delivers innovative and field-tested science and technology (S&T) solutions to address defence and security needs of the Alliance. Responsibilities: Design and implement complex algorithms using HDL (Verilog/VHDL) and collaborate with software teams to integrate FPGA components into complete system solutions Develop and verify SoC architectures (ARM + FPGA), including test benches, Linux kernel drivers, and hardware-software integration for embedded systems Participate in Agile ceremonies including sprint planning, daily stand-ups, retrospectives, backlog refinement, code reviews, and technical documentation using AzureDevOps or similar platforms Champion security compliance, Test-Driven Development (TDD), and quality assurance practices throughout the development lifecycle, ensuring adherence to industry standards and best practices Essential Qualifications & Experience: A minimum requirement of a bachelor’s degree at a nationally recognised/certified University in an information systems, physics or electronics related scientific or engineering discipline A minimum of 3 years of experience in HDL (Verilog, VHDL) for FPGA design, SoC architectures (ARM + FPGA) Professional experience in Linux kernel space programming for driver development and hardware-software integration. Strong experience with Agile/Scrum methodologies, Git workflows, code review processes, and collaboration tools (AzureDevOps, JIRA, GitHub, GitLab, etc.) Deep understanding of SDLC phases with proficiency in continuous integration/deployment practices, automated testing strategies, and iterative development approaches Solid grasp of SOLID principles, design patterns, and architectural approaches including Domain Driven Design (DDD), Test-Driven Development (TDD), and clean code practices Knowledge of secure coding practices, OWASP guidelines, vulnerability management, static/dynamic analysis tools, and commitment to writing maintainable, well-tested code with comprehensive unit, integration, and end-to-end testing Strong analytical and debugging skills with ability to break down complex problems, apply appropriate design patterns and refactoring techniques, communicate technical concepts to diverse audiences, and document solutions effectively Good level of spoken and written English If you've read the description and feel this role is a great match, we'd love to hear from you! Click "Apply for this job" to be directed to a brief questionnaire. It should only take a few moments to complete, and we'll be in touch promptly if your experience aligns with our needs.

Responsibilities

Design and implement complex algorithms using HDL and collaborate with software teams for FPGA integration. Develop and verify SoC architectures, including test benches and hardware-software integration for embedded systems.