Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a Front-End Methodology CAD Engineer, you will play a major role in promoting a reliable work environment for developing, maintaining, and improving automation software that design teams use for creating, modifying and analyzing RTL. Furthermore, you may support and develop RTL analysis applications like Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), and Lint applications for our SoCs across multiple design sites. In addition, you will have the opportunity to develop Generative AI solutions that the design team can use to improve experience working with these RTL Construction and Analysis applications.

DESCRIPTION

In this highly visible role, you will be: - Responsible for developing, maintaining and enhancing our automation flows for constructing and modifying RTL for our SoCs across multiple design sites - Responsible for developing, maintaining and enhancing our RTL Analysis Flows (RDC, CDC, Lint) application for our SoCs across multiple design sites - Responsible for writing Generative AI applications that enhance our RTL Construction and Analysis flows - Utilize your debugging experience to debug tool problems and collaborate with designers to help solve their problems - Work with EDA vendors to drive improvements and new methodologies

MINIMUM QUALIFICATIONS

• Minimum requirement of Bachelors Degree +3 years of relevant industry experience
• Experience in programming languages such as Perl or Python
• Experience in Verilog/System Verilog

PREFERRED QUALIFICATIONS

• Experience in Verific-based Verilog parsers and elaborator
• Demonstrated experience developing large-scale software system development from specification to deployment
• Demonstrated ability to take a spec, create software to meet it, develop the tests to validate the software, document the software, and support it with your customers
• Experience in Generative AI / LLM tools and applications
• Experience in RTL Analysis tools such as Reset-Domain-Crossing (RDC) and Clock-Domain-Crossing (CDC) methodologies
• Source control system management (Perforce, Git) is a plus
• Excellent communication, debug and root causing skills

Please refer the Job description for details