GPU Formal Design Verification Engineer at Apple

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

14 May, 26

Salary

0.0

Posted On

13 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Formal Verification, Property Checking, RTL Verification, Micro-architectural Details, Specification Review, Verification Plans, Formal Verification Reviews, Programming, Scripting, Verilog, System Verilog, SVA, Formal Tools, JasperGold, IFV, Abstraction Techniques

Industry

Computers and Electronics Manufacturing

Description

Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, you and your team will enable our customers to do all the things they love with their devices! The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification applying formal and property checking methods. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. DESCRIPTION In this role you will: - Work with the design team to review and enhance specifications. - Implement verification plans in coordination with design leads, verification leads and micro-architects. - Complete formal verification across multiple design blocks. - Conduct formal verification reviews with design and verification teams. MINIMUM QUALIFICATIONS BS degree in Computer Science, Computer Engineering, Electrical Engineering or equivalent field. Experience in programming/scripting languages. PREFERRED QUALIFICATIONS Knowledge of CPU or GPU design architectures, VLSI circuits, and digital logic design. Experience with HDLs such as Verilog/System Verilog and temporal logic assertion-based languages such as SVA. Exposure to formal verification and analysis of pipelined micro-architectures, MMUs, and cache coherency control mechanisms. Experience with formal tools, such as JasperGold, IFV, etc. Experience using academic formal verification tools. Understanding of abstraction techniques and formal verification technologies. Experience in reviewing and interpreting design specifications. Knowledge of constrained random verification methods. Ability to collaborate across teams.

Responsibilities

The engineer will be responsible for pre-silicon RTL verification using formal and property checking methods, requiring a deep understanding of GPU micro-architectural details. Key tasks include implementing verification plans, completing formal verification across multiple design blocks, and conducting formal verification reviews.