GPU Physical Design Engineer at Apple

Austin, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

14 May, 26

Salary

0.0

Posted On

13 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Chip Integration, RTL, Tapeout, PPA Optimization, Floorplanning, Static Timing Review, Physical Design Verification, Synthesis, DFT Insertion, Clock Distribution, Power Distribution, Place and Route, Timing Signoff, Electrical Signoff, Hierarchical Design

Industry

Computers and Electronics Manufacturing

Description

Do you love creating sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient GPU! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions! Joining this group means crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on experience in physical design and large chip integration, being responsible for implementing complete chip design from RTL to tapeout. DESCRIPTION - Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle. - Drive outstanding PD construction and optimization recipes for performance, power and Area (PPA). - Work on pioneering designs in the latest technology nodes. - Collaborate to drive methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress. - Drive the work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR. - Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution. MINIMUM QUALIFICATIONS BS + 3 years of relevant experience. Experience with one or more of the following: floorplanning partitions, conducting route and placement flow experiments, reviewing static timing, and physical design verification flow results. PREFERRED QUALIFICATIONS We value ability in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff. Work with FE teams to understand the design architecture to drive optimal floorplanning and physical implementation through early RTL feedback. Use design knowledge and innovative physical construction and optimization flows to push performance, power, and Area (PPA) of GPU designs. Experience with multi-voltage, power gated, and power retention will be an advantage. Practical knowledge with hierarchical design approach, top-down design, budgeting, timing, and physical convergence will be an asset. Experience on integrating IP from both internal and external vendors and able to specify and drive IP requirements in the physical domain. Depth of expertise with large GPU designs (>20M gates) with frequencies in excess of 1GHz applying brand-new technologies. Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal management.

Responsibilities

This role involves implementing complete chip designs from RTL to tapeout, requiring strategic engineering and hands-on physical design expertise for large, power-efficient GPUs. Responsibilities include driving physical design construction and optimization for PPA, collaborating on methodologies, and leading the resolution of physical design and flow issues.