Graduate Trainee- Silicon Design Engineer (RTL) at Advanced Micro Devices, Inc

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

05 Jul, 26

Salary

0.0

Posted On

06 Apr, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Digital Design, System Verilog, Verilog, Perl, TCL, Python, Processor Architecture, Debugging, Scripting, Simulation, Regression Management, High Speed IO Protocol, USB, PCIe, Ethernet

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Technology and Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the RTL and design related tasks of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD’s product portfolio resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and RTL design in general. You are a team player who has excellent communication skills, responsible and willing to pick new skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Understanding architecture specifications requirements and completing all duties assigned by the Supervisor. Able to work well inside team/cross functional team. Collaborate and communicate with team members to understand task that require to deliver. Run design flows, simulations and regression management. Perform first level debug test/design errors to determine the root cause. Suggest fixes and solutions to test/design errors Develop scripting for daily task execution efficiency improvement. PREFERRED EXPERIENCE: Knowing system Verilog, verilog , Perl, TCL, Phython is a plus. LOCATION: Penang, Malaysia #LI-DW2 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves planning, building, and executing RTL design tasks for High Speed IO Protocol IPs to ensure bug-free designs. Responsibilities also include running simulations, managing regressions, and developing scripts to improve task execution efficiency.