Graphics FE Implementation Engineer at Apple
Santa Clara, CA 95050, USA -
Full Time


Start Date

Immediate

Expiry Date

07 Nov, 25

Salary

190900.0

Posted On

08 Aug, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Design, Computer Architecture, Static Timing Analysis, Logic Design, Synthesis, Verilog

Industry

Information Technology/IT

Description

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish! Dynamic, resourceful people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join the team that optimizes and delivers world-class GPUs into Apple Silicon. As part of the GPU FE Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.

DESCRIPTION

Candidates will be responsible for RTL to netlist generation working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. Through this collaboration, you will deliver the best-in-class GPU’s for the best consumer products. If you’re ready to help chart the future of Apple Silicon, we’d love to talk to you.

MINIMUM QUALIFICATIONS

  • Relevant Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design
  • Experience with at least one scripting language (python/perl/tcl)
  • BS required

PREFERRED QUALIFICATIONS

  • Familiarity with Verilog and System Verilog
  • Exposure to industry standard rtl2gds tools for synthesis, place and route, static timing analysis
  • Exposure to Clock/Reset domain crossing or Voltage crossing principles
  • Familiarity with DFT methodologies
  • Knowledge of static timing analysis concepts (setup and hold timing)
  • Understanding of CMOS device characteristics for area/timing/power tradeoffs

How To Apply:

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Responsibilities

Please refer the Job description for details

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