Graphics Power Analysis & Optimization Engineer at Apple

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

13 Jul, 26

Salary

0.0

Posted On

14 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

GPU development, Power analysis, Micro-architecture, Python, PowerArtist, PTPX, RTL, Gate-level power analysis, Power optimization, ASIC design, Data mining, Power modeling, Post-silicon power correlation, Power management, SoC design

Industry

Computers and Electronics Manufacturing

Description

Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You’ll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you’ll be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices! We are looking for a talented and creative engineer to support the power activity of Apple best-in-class GPU development. DESCRIPTION For this role, the candidate must have strong analytical skills and background in power, micro-architecture and scripting to support the following activities on GPU designs: - Create early power estimation, power targets and perform what-if analysis at architectural evaluation stage. - Support RTL and gate-level power rollup and analysis. - Analyze various GPU workloads to identify power reduction opportunities. - Evaluate and implement power optimizations in both RTL and gates. - Identify the best power sign-off tests to improve power analysis coverage. - Develop flows & heuristics to accelerate power triage on large power data sets. MINIMUM QUALIFICATIONS Experience with low power microarchitecture and implementation. Experience with scripting in Python. Experience with PowerArtist and/or PTPX. BS degree and minimum of 10+ years of relevant experience. PREFERRED QUALIFICATIONS Experience in product level power budgeting and projection. Experience in writing, simulating and debugging RTL designs. Experience in low power ASIC design and implementation techniques. Experience in data mining applications to power modeling & triage. Experience in power use-case definition and analysis. Experience in post-silicon power correlation. Experience in power management techniques. Excellent communication skills, self-motivated and well organized.

Responsibilities

The engineer will perform early power estimation, power targets, and what-if analysis at the architectural evaluation stage for GPU designs. They will also analyze GPU workloads to identify power reduction opportunities and implement optimizations in both RTL and gates.