Job Description

Roles & Responsibilities

Main Responsibilities

• Lead board level architecture and schematic ownership for accelerator cards, modules, and test platforms.
• Design evaluation and bring up hardware for new ASICs/SoCs, including power rails, sensing, clocking, access ports, and instrumentation points.
• Define stackup, materials, impedance targets, and routing constraints for PCIe Gen4/5/6, DDR5, LPDDR5, GDDR, and 25G+ SerDes interfaces.
• Architect high current PDNs and multi phase VRMs at hundreds of amps, including sequencing, telemetry, and decoupling strategy.
• Drive first silicon bring up: power on, characterization, margining, and cross functional debug across hardware, firmware, and silicon.
• Use lab instrumentation such as oscilloscopes, high bandwidth probes, VNAs, BERTs, protocol analyzers, power analyzers, and thermal tools.
• Apply Python for lab automation, data capture, and measurement workflows.
• Oversee DFM/DFT/DFA, prototype builds, ECOs, BOM control, and vendor engagement through fabrication and assembly.
• Act as design authority in reviews, producing clear documentation, test plans, and alignment across silicon, firmware, mechanical, and manufacturing teams.

Qualifications

• 10+ years of board level high speed digital design experience.
• Direct schematic and architecture ownership within the last 3 years in Allegro System Capture, OrCAD/Altium, or Xpedition.
• One platform personally owned end to end from concept through volume production.
• One first silicon bring up where you designed the board powering up a new ASIC/SoC.
• Hands on experience defining stackup and routing constraints for PCIe Gen4+, DDR5, LPDDR5, GDDR, or 25G+ SerDes.
• Strong PDN and multi phase VRM design at high current levels, including PMBus and sequencing.
• Proficiency with lab instruments (oscilloscopes, VNAs, BERTs, protocol analyzers, power analyzers, thermal tools).
• Python scripting for lab automation and measurement processing.
• Solid understanding of DFM, DFT, DFA, and manufacturing processes.

Im afraid you would not be suitable for this role if you have:

• Program or system leads managing ODM executed designs.
• Engineers whose hands on design ended before ~2020.
• Sustaining, validation, or test engineers without board architecture ownership.

Apply Applicants meeting this criterion and looking for a progressive and challenging opportunity should submit an application via the apply link. If you have any further questions, you can reach out to EMAIL_ADDRESS, quoting the GWG reference - #15131

Desired Candidate Profile

10+ years of board level high speed digital design experience. Direct schematic and architecture ownership within the last 3 years in Allegro System Capture, OrCAD/Altium, or Xpedition. One platform personally owned end to end from concept through volume production. One first silicon bring up where you designed the board powering up a new ASIC/SoC. Hands on experience defining stackup and routing constraints for PCIe Gen4+, DDR5, LPDDR5, GDDR, or 25G+ SerDes. Strong PDN and multi phase VRM design at high current levels, including PMBus and sequencing. Proficiency with lab instruments (oscilloscopes, VNAs, BERTs, protocol analyzers, power analyzers, thermal tools). Python scripting for lab automation and measurement processing. Solid understanding of DFM, DFT, DFA, and manufacturing processes.

Im afraid you would not be suitable for this role if you have:

• Program or system leads managing ODM executed designs.
• Engineers whose hands on design ended before ~2020.
• Sustaining, validation, or test engineers without board architecture ownership.