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Hardware Engineer/ Senior Hardware Engineer II (Multiple Roles) - Azure Cor at Microsoft
Haifa, Haifa District, Israel -
Full Time

Start Date

Immediate

Expiry Date

19 Feb, 26

Salary

0.0

Posted On

21 Nov, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Hardware Design, Verification, System Verilog, UVM, ASIC Design, Test Plans, Communication Skills, Problem Solving, Leadership, Training, Software Development, System Architecture, Test Benches, Verification Infrastructure, Customer Requirements, Cloud-Grade Quality

Industry

Software Development

Description
Own and lead the development of complicated hardware units and test environments, based on deep understanding of customer requirements, functionality, and system architecture. Design and implement RTL in System Verilog, and VIP, test benches, and verification infrastructure in System Verilog UVM. Develop and execute test/coverage plans to verify hardware designs and reach cloud-grade quality. Interact with software developers and system-validation platforms, as part of the verification/validation flow. Oversee and train junior engineers and take leadership roles on large projects. Occasional on-call responsibilities for resolving customer issues in production. We're hiring for multiple roles for Logic Design Engineers, and Verification Engineers, on various levels, starting with 3 years of exprience 3+ years of proven experience in design and/or verification of large ASIC designs Knowledge of hardware design and verification concepts and tools (e.g., timing, pipelined design, UVM, Specman, unit level and full chip verification, coverage-based verification, formal verification) A versatile can-do, problem-solving attitude, and desire to handle a wide array of challenges. Excellent communication skills in English. BSc/MSc in Electrical Engineering, Computer Science, or Computer Engineering, from a major university.
Responsibilities
Own and lead the development of complicated hardware units and test environments. Interact with software developers and system-validation platforms as part of the verification/validation flow.