HSIO Functional Validation Engineer at NVIDIA

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

23 Dec, 25

Salary

0.0

Posted On

24 Sep, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

HSIO Functional Validation, Post Silicon Bringup, Power Optimisations, PCIe, USB, Interconnect Power Management, Electrical Tuning, Firmware Structures, Lab Debug, Silicon Bringup, Automation Scripting, Linux, Computer Architecture, Timing Analysis, Statistical Error Rates, Power Analysis

Industry

Herstellung von Computerhardware

Description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to resolve, that only we can seek, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. NVIDIA silicon solutions group is seeking hardworking engineers to be part of a post silicon HW team. As a member of this team, you will dive into next-gen high speed interconnects like PCIe, NVLink and C2C to plan and lead post silicon validation. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. What you’ll be doing: Develop strategies and infrastructure for next generation HSIO bring up, validation and product integration with a deep understanding of IO design, specs, use case and topologies. Ensure interoperability with connected devices and system components in complex interconnect topologies Deep dive into technically challenging HSIO bugs and help drive debug efforts across various teams Work on system level power strategies to continue pushing performance in power constrained systems Work closely and proactively with other engineering teams such as system architects, mixed signal and design, DGX, software/firmware, HW/SW QA, operations and AE teams to drive design, development, debug and release of next generations products. What we need to see: BS or MS degree in EE/CE or equivalent experience Minimum 2 years working in post-silicon bringup, HSIO Functional validation, and/or power optimisations. Experience with HSIOs like PCIE or USB including understanding of process/temp/voltage sensitivity on BER Experience with system level and interconnect power management optimisations. Understanding of electrical tuning/performance/challenges of HSIO Understanding of firmware/driver structures and their interaction with HW Hands-on validation lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analysers) Strong EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis. Excellent problem solving, teamwork, and interpersonal skills. Background with automation scripting in languages such as Perl, Python, tcl, Experience with Linux NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you. #LI-Hybrid NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

Develop strategies and infrastructure for next generation HSIO bring up, validation, and product integration. Ensure interoperability with connected devices and system components in complex interconnect topologies.