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IC Layout designer at Avicena Tech

Sunnyvale, California, United States -

Full Time

Start Date

Immediate

Expiry Date

11 Feb, 26

Salary

0.0

Posted On

13 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IC Layout Design, Mixed Signal CMOS, Tapeout, Physical Verification, Floor Planning, Custom Layout, Design Rules, Circuit Performance, EM Analysis, IR Analysis, DRC, LVS, ERC, Antenna, Post Layout Extraction, Cadence Virtuoso

Industry

Semiconductor Manufacturing

Description

Responsibilities: Delivering the entire chip layout to the committed timeframe and within the required design requirements. Being responsible for the entire chip Tapeout and physical verification. Complete layout and verification of analogue and mixed-signal designs using industry-standard CAD tools. Be responsible for floor planning, custom layout and verifying against design rules. Work closely with design engineers to achieve optimal circuit performance and produce high-quality layout designs. Ability to solve layout design problems and provide innovative solutions. Contribute to complex IC development projects and prepare documents for knowledge sharing. Proven record of completing tasks on time or ahead of schedule while maintaining quality. Qualifications: Minimum of 10 years of relevant mask design/layout experience in mixed signal CMOS IC layout design at block & chip top level, including chip floor planning and integration. Must have experience in handling full chip layout and integration using state-of-the-art IC layout tools like Cadence Virtuoso. Must have experience with FINFET process. Must have a deep understanding of analogue circuit layout concepts in submicron CMOS technologies, device matching, shielding, etc. Experience with EM & IR Analysis and fixing for the layout closure. Experience in DRC, LVS, ERC, Antenna, and post layout extraction using Pegasus/Calibre verification tools. Knowledge of foundry command deck, PDK, fabrication & mask process. Must have design management techniques to ensure quality and deliver on schedule.

Responsibilities

The IC Layout Designer will be responsible for delivering the entire chip layout on time and ensuring it meets design requirements. This includes tapeout, physical verification, and collaborating with design engineers for optimal circuit performance.