1-4 years of experience

Support Foundation IP development and release activities through RTL Verilog updates, quality assurance, and release management. Responsibilities include implementing and validating RTL design changes, managing ClearCase-based release processes, performing QA checks for Foundation IP deliverables, and enhancing release workflows through Python scripting and automation.

The role requires close collaboration across multiple global sites and cross-functional teams, with a strong focus on daily communication, coordination, and proactive issue resolution to ensure project milestones and release deadlines are met. The successful candidate will work with design, verification, integration, and program teams to deliver high-quality IP releases, improve process efficiency, and maintain configuration management and release documentation.

Must Have:

• RTL integration, ASIC design 2. CDC, Lint 3. Verilog/system verilog 4. AMBA protocols 5. scripting
• DesignSync
• Linux
• Scripting
• Verilog

Nice To Have:

• IP release flow
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