Please note this role is primarily open to candidates currently located in, and with working rights to Germany (preferably Munich, Berlin or Dresden).

• Develop and Utilize Transaction-Level Models (TLMs): Design, adapt, and maintain high-quality TLMs (primarily using C++ / SystemC) for peripherals, memory subsystems, and other SoC components to build comprehensive virtual platforms centered around Codasip RISC-V IPs.
• Drive SoC Integration for Codasip RISC-V IPs: Employ TLMs to integrate Codasip RISC-V IPs with diverse external components, enabling robust in-situ IP evaluation and facilitating rapid prototyping of customer-representative SoCs.
• Enhance RISC-V IP Evaluation in SoC Contexts: Advance our Exploration Framework by integrating sophisticated TLM-based environments to showcase the performance and capabilities of Codasip RISC-V cores under realistic SoC workloads.
• Create and Refine SoC-Level Mocking Capabilities: Contribute to our initiatives for developing TLM-based mocking of external modules. This will allow defining descriptive input/output and processing behaviors, enabling early software development on virtual platforms incorporating Codasip RISC-V IPs.
• Model Memory Subsystems for RISC-V SoC Performance Analysis: Utilize TLMs to accurately model various memory interfaces (e.g., DDRx, LPDDRx) and hierarchies (caches), simulating their impact on overall system throughput and IP behavior within an SoC.
• Analyze and Optimize RISC-V based SoC Performance: Leverage TLM-based simulations to gain deep insights into IP behavior within an SoC, identify performance characteristics, and provide actionable feedback to IP design teams and customers.
• Support Codasip IP Deployment: Act as a key resource for our IP teams and field application engineers, providing expert guidance and utilizing TLM environments to help demonstrate, enhance, and ensure successful integration of Codasip IPs into customer SoCs.