Intern, Physical Design Engineer - Chiplets at Tenstorrent

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

22 Apr, 26

Salary

70.0

Posted On

22 Jan, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Timing Reports, Power Grids, Clock Trees, Layout Blocks, Chiplets, Collaboration, Feasibility Studies, Problem-Solving, Flow Efficiency, Automation

Industry

Computer Hardware Manufacturing

Description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're building fast silicon and integrating it into a chiplet-based system — and we need people who can help close that loop. This isn’t just a PnR role — it’s about owning the last mile between great architecture and real silicon. If you know physical design or want to level up fast in it, and care about making hard things work, we’ve got room at the table.This role is remote based out of North America. This role is onsite, based out of Santa Clara, CA. Who You Are Deeply curious about how high-performance silicon gets built and delivered. Comfortable in the weeds—handling timing reports, power grids, clock trees, and layout blocks. Interested in how chiplets change physical design, integration, and packaging. A builder who sees constraints as part of the fun, not a reason to back off. What We Need Expertise in the physical implementation flow, spanning RTL to physical silicon via synthesis, P&R, timing, and signoff for clean chiplet integration. A strong collaborator capable of aligning physical implementation with architectural and verification intent. Ability to perform feasibility studies of fundamental paths in the CPU A practical problem-solver who improves flow efficiency, automates repetitive tasks, and catches issues early What You Will Learn How chiplet architecture reshapes the rules of physical design and timing What it takes to build a system where the silicon, packaging, and performance all align Why real closure isn’t about tools—it’s about understanding the system How a tightly integrated team moves fast across disciplines and tapeouts Compensation for all interns at Tenstorrent ranges from $50/hr - $70/hr including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made. Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

Responsibilities

The role involves owning the last mile between architecture and silicon, focusing on physical implementation and integration of chiplets. The intern will work on timing, power grids, and layout blocks to ensure efficient design.