[INTERNSHIP] Flow Development Support for STA 2026 at SiPearl

Castelldefels, Catalonia, Spain -

Full Time

Start Date

Immediate

Expiry Date

08 Jun, 26

Salary

0.0

Posted On

10 Mar, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, Timing ECO, Physical Design, Automation Scripts, Timing Reports, Timing Violations, Timing Closure, EDA Tools, Synopsys PrimeTime, Fusion Compiler, StarRC, Tcl, Shell, Python, Linux, Git

Industry

Semiconductor Manufacturing

Description

❓ About SiPearl… SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint. In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France. Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in : France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis), Spain (Barcelona) and Italy (Bologna) Following a €130 million Series A, the company has launched its Series B round. 🎯Missions SiPearl is developing next-generation high-performance and energy-efficient processors. To contribute to this effort, you will join the physical design team to support the development and improvement of flows related to Static Timing Analysis (STA) and Timing ECO. Working closely with physical design and methodology engineers, you will contribute to improving automation, robustness, and efficiency of timing analysis and optimization flows used in large-scale CPU designs. In this internship you will: Understand the timing analysis methodology and the existing Static Timing Analysis flows used in advanced SoC designs. Support the development and improvement of PrimeTime-based STA and Timing ECO flows, including automation scripts and flow infrastructure. Contribute to the development of tools and scripts to analyze timing reports and facilitate debugging of timing violations. Assist in the implementation and evaluation of Timing ECO flows to fix setup/hold violations and optimize timing closure. Participate in trial runs and analyze results to ensure flow robustness and correctness. Work with industry-standard EDA tools for Digital IC Design Implementation including but not limited to Synopsys tools (e.g. Fusion Compiler, PrimeTime, StarRC, etc.) Document the flow architecture, methodology, and results to support team knowledge sharing. 🔍What makes you a good match for the role Student in the final year of a Bachelor’s degree or pursuing a Master’s degree in electronics, microelectronics, computer engineering, or VLSI design. Basic understanding of digital design and RTL-to-GDS flows. Knowledge of Static Timing Analysis (STA) fundamentals and timing concepts (setup, hold, timing paths, constraints). Familiarity with scripting languages such as Tcl, Shell, or Python for flow automation. Exposure to EDA tools such as Synopsys PrimeTime, or other timing analysis tools, is a plus. Comfortable working in a Linux environment. Experience with Git-based version control is appreciated. Strong analytical skills and interest in automation and methodology development. Good written and spoken English for technical communication. 📍 Location -> Castelldefels

Responsibilities

The intern will support the physical design team by improving automation, robustness, and efficiency of Static Timing Analysis (STA) and Timing ECO flows used in large-scale CPU designs. This involves developing and improving PrimeTime-based flows, creating scripts for timing report analysis, and assisting with the implementation of Timing ECO flows to resolve violations.