IO Design Architect, HBM at Micron Technology

Seoul, , South Korea -

Full Time

Start Date

Immediate

Expiry Date

02 Jan, 26

Salary

0.0

Posted On

04 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

High-Speed IO Design, Clocking Design, IO Timing Budgeting, IO Design Principles, Off-Chip Protocols, Communication Skills, FinFET Device Characteristics, Signal Integrity, Channel Characteristics, ESD Design Techniques, Problem-Solving Skills, Analytical Skills, Circuit Debug Experience, D2D Design Experience

Industry

Semiconductor Manufacturing

Description

The High-Performance Integrated Group (HIG) is a division within the Technology and Products Group (TPG). We are dedicated to developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications! Our ultimate goal is to deliver the lowest power per bit solutions in the industry! Position Overview: We are looking for an HBM IO Architecture Design engineer own the development of the PHY IO on the interface die in HBM products. In this position, you will be responsible for the development including defining design target, developing spec, architecting IO/clocking/datapath, being responsible for design, optimization, and verification. Use of both analog and digital CMOS design skills will be needed to work on the various circuits you would be responsible for. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. Responsibilities will include, but are not limited to: High-speed IO design architecture for HBM products Planning IO development on next generation products, set design target of each IO and IO related block Work with Product Engineering to correlate silicon measurements and simulation performance for circuit level design analysis Contribute to cross group communication to work towards standardization and group success Proactively solicit guidance from Standards, CAD, modeling, and verification groups to ensure the design quality Drive innovation into the future Memory generation with dynamic work environment Successful candidates for this position will have: Prior industrial experience in high-speed clocking design at 16Gbps+ speed Prior experience in system level IO timing budgeting Proven knowledge of IO design principles for practical design tradeoffs on speed/area/power/complexity Familiar with one or more off-chip protocols such as UCIe, HBM, DDR, PCIe, MIPI, etc Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written Good understanding on FinFET device characteristics and hands-on design experience Deep understanding of signal integrity, channel characteristics, and ESD design techniques and topologies Excellent problem-solving and analytical skills Prior circuit debug experience through Product Engineering or equivalent preferred D2D design experience is a plus Required Experience: MS or PhD in EE Minimum 10+ years of proven experience in relevant Engineering or Design Engineering experience Job title and level can scale depending on experience and qualifications

Responsibilities

The role involves developing the PHY IO on the interface die in HBM products, including defining design targets and optimizing designs. Collaboration with a multi-functional team is essential to ensure the success of the HBM roadmap.