IP Design engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

28 Apr, 26

Salary

0.0

Posted On

28 Jan, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IP Level ASIC Design, RTL Code, Debugging Firmware, Verilog, System Verilog, C, C++, UVM Testbenches, Linux, Windows, AXI Protocol, Automating Workflows, Scripting Languages, Perl, Ruby, Makefile, Shell

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: It's a IP Designer role. The focus of this role is to plan, build, and execute the RTL design work of new and existing features for AMD’s MMHUB IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware/DV engineers, and firmware engineers to understand the new features to be designed Build design MAS documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature RTL and any required changes to the RTL codes Work with DV engineer to debug test failures to determine the root cause; work with firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics – help DV to modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC design work Proficient in RTL code and debugging firmware Experienced with Verilog, System Verilog, C, and C++ Known in using UVM testbenches and working in Linux and Windows environments AXI protocal knowledge Automating workflows in a distributed compute environment. Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset ACADEMIC CREDENTIALS: Masters degree in computer engineering/Electrical Engineering #LI-EH1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves planning, building, and executing RTL design work for AMD’s MMHUB IP, ensuring a bug-free final design. Collaboration with architects, hardware/DV engineers, and firmware engineers is essential to understand and implement new features.