Start Date
Immediate
Expiry Date
07 Aug, 26
Salary
0.0
Posted On
09 May, 26
Experience
10 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
RTL Design, UCIe, System Verilog, Verilog, CDC/RDC Analysis, Synthesis, Static Timing Analysis, Linting, Micro-architecture, SoC Architecture, High-speed Protocols, Formal Checking, Debugging, Technical Leadership, P&R Interactions, VHDL
Industry
Semiconductor Manufacturing