Start Date
Immediate
Expiry Date
21 Aug, 26
Salary
0.0
Posted On
23 May, 26
Experience
10 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
RTL Design, UCIe, SystemVerilog, Verilog, CDC/RDC Analysis, Synthesis, Static Timing Analysis, Linting, Micro-architecture, SoC Architecture, High-speed Protocols, Digital IC Design, Formal Checking, P&R Interactions, Debugging, Technical Leadership
Industry
Semiconductor Manufacturing