Lead Design Verification Engineer at Altera

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

05 Jun, 26

Salary

0.0

Posted On

07 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Functional Logic Verification, FPGA, Verification Plans, Test Benches, Verification Environment, System Simulation Models, Power Analysis, Timing Analysis, Debugging, Pre-Silicon Validation, OVM/UVM, System Verilog, Constrained Random Verification, Protocol Verification, DDR, GPIO

Industry

technology;Information and Internet

Description

Job Details: Job Description: Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications. Qualifications: Minimum Qualification: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/with: Pre Silicon Validation/Verification. OVM/UVM, System Verilog, constrained random verification methodologies. Protocol verification experience of DDR and GPIO Preferred Qualification: Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in FPGA architecture or FPGA prototyping Job Type: Regular Shift: Shift 1 (Malaysia) Primary Location: Penang 15, Penang, Malaysia Additional Locations: Bengaluru, Karnataka, India, New Delhi, India (Remote) Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

The role involves performing functional logic verification of an FPGA to ensure it meets specification requirements by developing verification plans, test benches, and simulation models. Responsibilities also include executing verification plans, debugging issues in the pre-silicon environment, and collaborating with architects and developers to improve verification methodologies.