Required Qualifications:

• Strong experience in ASIC or FPGA design and simulation using Verilog/SystemVerilog
• Strong experience with synthesis, constraints, timing analysis, clock domain crossing.
• Strong experience with AMD(Xilinx) or Altera FPGAs and tools.
• Collaborative team player who works effectively with cross-functional groups and contributes to multi-designer projects.
• Clear, robust, and well commented coding style.
• Strong problem solving, troubleshooting, and debugging skills.
• Thorough and detail-oriented approach.
• Excellent verbal and written communication skills.

Required Qualifications:

• Strong experience in ASIC or FPGA design and simulation using Verilog/SystemVerilog
• Strong experience with synthesis, constraints, timing analysis, clock domain crossing.
• Strong experience with AMD(Xilinx) or Altera FPGAs and tools.
• Collaborative team player who works effectively with cross-functional groups and contributes to multi-designer projects.
• Clear, robust, and well commented coding style.
• Strong problem solving, troubleshooting, and debugging skills.
• Thorough and detail-oriented approach.
• Excellent verbal and written communication skills.