Company Overview
Red 6 is an innovative Augmented Reality (AR) technology startup leading the way in synthetic air combat training. Our primary technology, supporting our ATARS product, enables pilots to simulate the cognitive challenges of flying while accessing realistic, scalable training in dynamic outdoor environments.

EXPERIENCE, SKILLS, AND REQUIRED QUALIFICATIONS

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field (Master’s degree preferred).
• Experience: Minimum 10 years of FPGA design and development experience, with proven leadership on complex, multi-FPGA projects.
• Languages: Expert in Verilog, VHDL, and SystemVerilog; skilled in scripting (Python, TCL); proficient in C/C++ for hardware/software interaction.
• Tools: Advanced experience with Xilinx/AMD FPGA development tools (Vivado, Vitis), simulation tools, and version control systems.
• Protocols: In-depth knowledge of high-speed serial interfaces, PCIe, Ethernet, Aurora, Interlaken, UART, SPI, I2C, QSPI, and DDR memory interfaces.
• System Skills: FPGA architecture planning, part selection, power/resource estimation, and system-level integration.
• Strong communication skills for technical leadership across disciplines and with stakeholders.
• Ability to obtain a U.S. security clearance (U.S. citizenship required).

NOTE

Red 6 reserves the right to change its current benefits program at any time, in a manner that is consistent with applicable federal and state regulations.
This job description is not a contract and confers no contractual rights, privileges, or benefits on any applicant or potential applicant. Red 6 has the right to change any and all terms of this job description, including, but not limited to, job responsibilities, qualifications, and benefits. Nothing in this job description constitutes an offer or guarantee of employment.
Red Six Aerospace, Inc, is an Equal Opportunity Employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability status, protected veteran status, or any other characteristic protected by law.
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Compensation Range: $160K - $190

THE ROLE

We are seeking an experienced and highly capable Lead FPGA Engineer to architect, design, and deliver advanced FPGA solutions for our AR-based training systems. This role blends hands-on technical execution with leadership responsibilities, ensuring FPGA designs meet performance, scalability, and integration goals while mentoring and guiding the FPGA engineering team.
The ideal candidate will have deep expertise in FPGA development for complex systems, including multi-FPGA architectures, high-speed interconnects, and integration with both embedded and soft-core processors.

KEY RESPONSIBILITIES

• Lead architecture, design, and verification of FPGA-based systems for the ATARS product line.
• Design for multi-FPGA systems, including high-speed FPGA-to-FPGA communication protocols such as Ethernet, Aurora, and Interlaken.
• Develop and integrate FPGA designs utilizing embedded ARM cores and soft-core processors (MicroBlaze).
• Define FPGA part selection criteria and lead pinout definition in collaboration with the electrical engineering team.
• Participate in schematic reviews to ensure FPGA integration meets system requirements.
• Define FPGA system requirements, interface specifications, and architecture in collaboration with cross-functional teams.
• Oversee synthesis, timing closure, and resource/power optimization for high-performance FPGA designs.
• Drive design reviews, code quality standards, and verification strategies for the FPGA team.
• Lead integration and bring-up of FPGA hardware with embedded software and system components.
• Provide mentorship and technical leadership, ensuring team members follow best practices.
• Maintain up-to-date knowledge of FPGA technologies, tools, and methodologies to influence design decisions.
• Prepare and maintain comprehensive design documentation, including architecture diagrams, specifications, and verification reports.