Logic Design Engineer at Altera

Haifa, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

28 Mar, 26

Salary

0.0

Posted On

28 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Logic Design, RTL Development, Simulation, Mixed-Signal Design, Performance Optimization, Verification, Customer Support, SerDes Design, PHY Design, Firmware Implementation, Communication Standards, Digital Signal Processing, Debugging, Architecture Definition, Circuit Simulation, Power Optimization, Timing Analysis

Industry

technology;Information and Internet

Description

Job Details: Job Description: Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance. We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs. In this role, you will: Design and Develop: Create logic design, RTL, and simulation for IP blocks, functional units, and subsystems. Architectural Contribution: Participate in defining architecture and microarchitecture features for the designed block. Mixed-Signal Expertise: Apply advanced strategies, tools, and methods for mixed-signal designs, including analog behavior modeling and circuit simulation, to write RTL and optimize logic. Performance Optimization: Ensure designs meet power, performance, area, and timing goals while maintaining integrity for physical implementation. Verification and Quality Assurance: Review verification plans, validate design features, and implement corrective measures for failing RTL tests. Customer Support: Collaborate with SoC customers to ensure seamless integration and high-quality IP delivery. Qualifications: Minimum of 10 years of industry experience delivering complex, high-performance integrated solutions and driving them through mass production. Proven expertise in SerDes and PHY design, including RTL development and firmware implementation, is highly advantageous. Strong background in interfacing with communication standards and optimizing serial link chip architectures for power, performance, and area targets. Hands-on post-silicon experience in validating and refining design outputs through debugging and corrective measures. Additional experience contributing to system architecture definition and applying digital signal processing techniques is considered a plus. B.Sc. or M.Sc. in Electrical Engineering. Job Type: Regular Shift: Shift 1 (Israel) Primary Location: Haifa, Israel Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. About Altera Altera: Accelerating Innovators Altera provides leadership programmable solutions that are easy-to-use and deploy in applications from cloud to edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Altera is helping to shape the future through pioneering innovation that unlocks extraordinary possibilities for everyone on the planet. Don't see the dream job you are looking for? Click "Get Started" below to drop off your contact information and resume and we will reach out to you if we find the perfect fit.

Responsibilities

The Logic Design Engineer will design and develop logic designs, RTL, and simulations for IP blocks and subsystems. They will also ensure designs meet power, performance, area, and timing goals while collaborating with SoC customers for high-quality IP delivery.