Mask Layout Design Engineer - New College Graduate 2026 at NVIDIA

Shanghai, Shanghai, China -

Full Time

Start Date

Immediate

Expiry Date

19 Dec, 25

Salary

0.0

Posted On

20 Sep, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mask Layout Design, Digital IPs, Low-Power Circuits, High-Performance Circuits, Cadence Virtuoso, Siemens Calibre, Synopsis ICV, Communication Skills, Problem-Solving Skills, Analytical Skills, Scripting Ability, FinFET Processes, Standard Cells, Memory Structures, Team Collaboration, Verification Development

Industry

Computer Hardware Manufacturing

Description

NVIDIA has continuously reinvented itself over decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to tackle, that only we can pursue, and for that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing custom digital IPs. You will have the chance to learn novel low-power and high-performance circuits and you will showcase your layout design talent at the latest and smallest process node at the earliest time. We are now looking for Mask Layout Designers, NCG. If someone who desires to join a dynamic group of diverse individuals responsible for dealing with high-speed digital IP layouts, do not miss this opportunity. What You'll Be Doing: Physical layout of STD cells, ROMs, and compiled RAMs on each most advanced foundry processes with earlier and unstable design environments. Work closely with NVIDIA talents to speed up layout production including customized DRC/LVS, and plenty of specific verification development, testing, and debug. What We Need To See: Pursuing MS or PH.D. in MS Microelectronics, Semiconductor Physics or related field. You are familiar with Cadence Virtuoso, you're familiar with Siemens Calibre or Synopsis ICV, or similar design and verification tools. Experience working across teams and dealing the tasks in parallel. Excellent communication, problem-solving, and analytical skills to decompose complex issues and present them clearly and simply. Ways To Stand Out From The Crowd: Knowledge of and experience with advanced FinFET/GAA processes Prior design experience involving Standard Cells and/or Memory structures Good English written, verbal, and presentation skills Scripting ability in SKILL and/or Perl We are widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us and, due to outstanding growth, our exclusive engineering teams are rapidly growing. If you are a creative and autonomous engineer with a real passion for technology, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

The role involves the physical layout of standard cells, ROMs, and compiled RAMs on advanced foundry processes. You will collaborate with engineers to enhance layout production and develop specific verification tools.