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Master Thesis: Ethernet Switch Optimization for Energy-sensitive Deployment at Ericsson

Stockholm, , Sweden -

Full Time

Start Date

Immediate

Expiry Date

17 Feb, 26

Salary

0.0

Posted On

19 Nov, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Ethernet Switch Optimization, Processing Pipeline Optimization, ASIC Design, RTL Integration, RTL HDL Coding, Verilog, VHDL, Testbench Design, SystemVerilog, Scripting Languages, EDA Tools, Tcl, Python

Industry

Telecommunications

Description

Processing pipeline optimization (e.g. shift registers optimization) Deliver first-pass and second-pass power optimization solution packages, with quality of results validation by the BE team, towards the corresponding IP teams for RTL integration Currently pursuing a MSc in Electrical/Computer Engineering, Computer Science or similar. Experience in ASIC design and development. Skills in RTL HDL coding (such as Verilog or VHDL). Basic testbench design, preferably using SystemVerilog. Knowledge of scripting languages for EDA tools (Tcl, Python). The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world's toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. learn more. Primary country and city: Sweden (SE) || Stockholm Req ID: 773743

Responsibilities

The role involves optimizing processing pipelines and delivering power optimization solution packages. The candidate will validate results with the BE team and work towards RTL integration with corresponding IP teams.