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Master Thesis: Subsystem Reference Model at Top Level Verification at Ericsson

London, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

15 Jan, 26

Salary

0.0

Posted On

17 Oct, 25

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

C/C++, SystemVerilog, TLM, SystemC

Industry

Telecommunications

Description

Knowledge in the following: C/C++, SystemVerilog, TLM, SystemC. Currently pursuing a Msc level degree in: The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world's toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. learn more. Primary country and city: Sweden (SE) || Lund Req ID: 773641

Responsibilities

The role involves developing a subsystem reference model at the top level verification. You will be challenged to push the boundaries of what's possible and build innovative solutions.