Memory Chip Design Engineer at Western Digital

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

19 May, 26

Salary

194400.0

Posted On

18 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Memory Chip Custom Layout, Architecture Definition, Density Optimization, Performance Optimization, Final Verification, Tape Out, Physical Verification, DRC, LVS, ERC, Antenna Checks, Timing Analysis, Power Consumption Analysis, Reliability Engineering, Electromigration, IR Drop

Industry

Computer Hardware Manufacturing

Description

Company Description At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. This job opportunity is in Western Digital Research organization. We are a organization comprising of almost 100 Scientists with PhDs in Physics, Electrical Engineering, Computer Science and Materials science, focused on research and development of various future technologies. In addition to supporting magnetic storage and memory roadmap of Western Digital, we are focused on several key areas that are well aligned with our existing experimental and theoretical skills, and existing laboratory facilities. Job Description The job opening is for a full-time Research Staff Member in the Design Group in Western Digital's research department. The role will be a part of a multi-functional team whose aim is to develop and eventually commercialize Western Digital's strategic radiation hardened memory technology. The responsibilities for the role will include: Developing high density memory chip custom layout Including shared operational circuitry along with at pitch line drivers All phases of chip design layout to be included: From architecture definition, density and performance optimization, final verification up to and including tape out Running and Debugging Physical Verification flows including DRC, LVS, ERC and Antenna Checks Minimize parasitic resistance and capacitance (R and C) in critical paths to meet timing and power consumption specifications Comprehend and address reliability engineering issues such as electromigration, IR Drop and Design For Manufacturing robustness Coordination of a Split-Fab Design and Development between WD (for Memory Array Layers) and a CMOS Foundry (for Operational Circuitry) Developing and Harmonizing CMOS Foundry wafer requirements to allow for continued processing of Memory Array layers in WD’s Fabrication Line Development of EDA Tool Design Rules for WD’s Memory Array Layers Defining and executing the split-fab tape out flow Qualifications Minimum of a Bachelor's, Master's or PhD degree in Electrical Engineering, Physics, or closely related field. The prior track record of a viable candidate must show: Previous design layout, tape out and validation of high density memory chip designs Capability to develop design layout schedules that meet chip functional requirements and timelines Proficiency in Cadence Virtuoso (VXL), Mentor Graphics Calibre, or Synopsys IC Validator Capability to work closely with circuit designers to iterate on schematics and with process engineers to understand fabrication constraints Deep understanding of CMOS fabrication processes, Phase-Shift Mask Development and Multi-Patterning Techniques The following skills and experiences are highly desired Experience developing memory cell models for inclusion in simulation tool environment, such as Verilog-A Experience with emerging memories such as MRAM, ReRAM, or PCM Experience developing Radiation Tolerant Layouts Track record of publications and patents related to memory design layout Additional Information Western Digital is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. Western Digital thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Western Digital is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 01/14/2025 (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. Compensation & Benefits Details An employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future. If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws. You may also be eligible for shift differential pay, depending on the shift to which you are assigned. You will be eligible to be considered for bonuses under either Western Digital’s Short Term Incentive Plan (“STI Plan”) or the Sales Incentive Plan (“SIP”) which provides incentive awards based on Company and individual performance, depending on your role and your performance. You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Western Digital’s Standard Terms and Conditions for Restricted Stock Unit Awards. We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program; employee stock purchase plan; and the Western Digital Savings 401(k) Plan. Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company’s sole discretion, consistent with the law. Notice To Candidates: Please be aware that Western Digital and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests, please report it immediately to Western Digital Ethics Helpline or email [email protected]. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Salary Range: 145,800.00-194,400.00 Business Function: ASIC Development Engineering Work Location: San Jose Great Oaks Headquarters--LOC_WDT_USCA23

Responsibilities

The role involves developing high-density memory chip custom layouts, including shared operational circuitry and line drivers, covering all design phases from architecture definition to final tape out. Responsibilities also include running physical verification flows, minimizing parasitic resistance and capacitance in critical paths, and addressing reliability engineering issues.