Memory Hardware Engineer II at Microsoft

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

29 May, 26

Salary

199000.0

Posted On

28 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Dram, Dimm, Cxl, Firmware, Telemetry, Automation, Root Cause Analysis, C/C++/Rust, Python/Powershell, Data Analytics, Schematics, Datasheets, Diagnostics, Ci, Cloud Reliability, Hardware Lifecycle

Industry

Software Development

Description

Overview Support Azure’s memory products—including DRAM, DIMM, CXL, and AI server memory—by developing code, automation, and tools to keep our cloud fleet reliable and cutting-edge. As a Memory Hardware Engineer II on the Azure Memory & Storage team, you’ll play a hands-on role supporting Azure’s growing fleet of compute, AI, and other servers in the cloud. You’ll develop and maintain processes, support tools, and automation infrastructure to ensure the health and freshness of memory products—including CXL-based devices. This role blends hardware expertise with software development: you’ll build telemetry pipelines, automate firmware updates, and drive root-cause analysis for memory subsystem issues. You’ll collaborate with support, OS, and partner teams, turning data into action and making a real impact on cloud reliability. Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Azure Memory & Storage Center of Excellence (AMS CoE) is part of the SCHIE organization focusing on Memory and Storage devices going into cloud hardware servers of all varieties. AMS provides memory and storage solutions to Azure, drives memory and storage suppliers to deliver high quality products meeting Microsoft requirements. We are looking for a Memory Hardware Engineer II with a passion for driving impact through optimizing products and processes for quality, reliability, cost, and performance. Responsibilities Collaborate to maintain CXL firmware freshness across labs and fleet (tracking versions, compliance, rollouts, and guardrails). Collaborate to implement and operate telemetry flows for CXL devices (collection, storage, data sharing, and reporting). Develop automation and tooling for memory hardware lifecycle in collaboration with other teams. Identify, triage, and resolve memory‑subsystem faults; drive end‑to‑end root cause with cross‑team partners and implement fixes. Contribute code and documentation to firmware, diagnostics, and test harnesses; improve developer ergonomics and CI. Qualifications Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 2+ years technical engineering experience OR equivalent experience. Preferred: Memory hardware or related experience Proficiency with C/C++/Rust or other lower-level programming languages Memory subsystems and interfaces (e.g., DDR/CXL) foundational experience; comfort with schematics and datasheets. Practical scripting in Python/PowerShell for automation. Experience with data analytics, data collection/aggregation, and dashboarding. Ability to trace issues across firmware, drivers, and OS; written/verbal communication with partner teams. Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Hardware Engineering IC3 - The typical base pay range for this role across the U.S. is USD $100,600 - $199,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $131,400 - $215,400 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Responsibilities

This role involves supporting Azure’s memory products by developing code, automation, and tools to maintain cloud fleet reliability, focusing on CXL-based devices. Responsibilities include collaborating on CXL firmware freshness, implementing telemetry flows, developing automation, and driving end-to-end root cause analysis for memory subsystem faults.