Memory Subsystem Enablement Verification Engineer at Advanced Micro Devices, Inc

Ottawa, Ontario, Canada -

Full Time

Start Date

Immediate

Expiry Date

07 Aug, 26

Salary

0.0

Posted On

09 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

C, C++, System Verilog, UVM, Python, System C, DDR/JEDEC Standards, Zebu Emulation, Hardware/Firmware Co-verification, SVA/OVL, Git, Perforce, Testbench Architecture, Functional Coverage, Memory Controller Verification, DPI-C

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: The Memory Subsystem team is looking for passionate and experienced pre-silicon Verification engineers for the pre-silicon readiness of high-speed LPDDRx, DDRx and associated IPs through the utilization of advanced co-simulation hybrid environments. The individual will be part of a high performing team that focuses on all things DDR to shift left productization. Be a part of the definition, design, and development phase of industry-leading memory subsystem end to end solution. THE PERSON: Are you looking to take on and tackle advanced engineering challenges with advanced environments? We are looking for open minded, flexible, innovative, and creative engineers seeking to join a new team to develop an end-to-end verification solution from IP/subsystem design and verification through advanced technics. End to end involves architecture through production. We are also looking for strong interpersonal and communication skills – this position will be working collaboratively across the AMD organization! Are you looking for a ground floor opportunity to drive real advancements that positively impacts the company? If this sounds like you, please apply! KEY RESPONSIBILITIES: Excellent knowledge of C, C++, System Verilog Experience in ground-up development and verification with IP and Subsystem verification Advanced testbench architecture, microarchitecture, development, and implementation experience, including co-verification In depth knowledge of code and functional coverage constructs as well as test plans to coverage relationships Development and debug of co-verification environment with production level firmware Development and maintenance of test suite through firmware feature set modification as well as custom transactor-based stimulus development Subsystem and block level test plan development in relationship to FW/HW co-verification and maintenance as well as subsystem test plan development Ability to adapt and learn new toolsets and framework, making updates as needed PREFERRED EXPERIENCE: Knowledge and development of monitors and checkers and/or experience developing SVA/OVL and synthesizable assertions Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller verification. UVM object-oriented design Understanding and experience utilizing architectural models Knowledge of System C and Python Zebu Emulation verification and debug experience Experience in hardware/Firmware co-verification in UVM System Verilog, C-DPI, and gasket structured testbench Memory VIP integration, initialization, and debug experience End to end verification experience from front end verification through lab bring up Strong understanding of synchronization techniques (handshakes, message passing); knowledge of hardware level clocking and multi-domain simulation synchronization Strong knowledge of GIT and perforce Development and maintenance of regressions as well as coverage databases. SoC IP knowledge and architectural understanding of the purpose of each IP ACADEMIC CREDENTIALS: Bachelor’s degree in electrical or computer engineering and relevant experience, or Master's or PhD degree in Electrical or Computer Engineering with relevant experience. #LI-DP1 #LI-HYBRID Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Develop and implement pre-silicon verification solutions for high-speed memory subsystems using advanced co-simulation hybrid environments. Focus on end-to-end verification from IP design through production, including the development of test plans and firmware co-verification.