Mixed Signal Design Engineer (RDSS Intern) at NVIDIA

Taipei, , Taiwan -

Full Time

Start Date

Immediate

Expiry Date

09 Apr, 26

Salary

0.0

Posted On

09 Jan, 26

Experience

0 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mixed-Signal Design, Analog Circuit Design, High Speed Memory I/O Interfaces, Deep Submicron CMOS, FinFET Processes, Interpersonal Skills, Device Reliability, ESD Requirements, Latch-Up Requirements, Layout Development, Circuit Design, Cadence Tools, Circuit Simulators, Verilog, Matlab, Lab Test Equipment

Industry

Computer Hardware Manufacturing

Description

By submitting your resume, you’re expressing interest in our 2026 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role. We are looking for a Mixed-Signal/Analog/IO Circuit Design Engineer (RDSS Intern) – someone who is excited to join a growing group of diverse individuals responsible for handling challenge high-speed memory interface designs. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. What you'll be doing: Mixed-Signal/Analog circuit design for High Speed Memory I/O Interfaces Solve challenge of circuit designs in deep submicron CMOS FinFET processes Take designs through productization and be involved in all stages of development Work with multi-functional teams to optimize the designs What we need to see: MSEE or equivalent experience. A teammate with good interpersonal skills System level timing budgets, specs and analysis In-depth understanding of deep submicron CMOS FinFET process and circuit design issues Familiarity with device reliability, ESD and Latch-Up requirements Supervise layout development and understand all ESD/Latch-Up, reliability rules Broad circuit design and implementation knowledge with significant depth Working Knowledge of package substrate, board design and power delivery is a plus. Background with Cadence custom design tools, various circuit simulators like Hspice, XA, FineSim, Spectre Working knowledge of Verilog, Nanotime, Matlab is plus along with hands on with Lab test and measurement equipment is a plus We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

The intern will be involved in mixed-signal and analog circuit design for high-speed memory I/O interfaces and will solve challenges related to circuit designs in deep submicron CMOS FinFET processes. They will also work with multi-functional teams to optimize designs and take them through productization.