Mixed-Signal IC Verification Engineer at Elevate Semiconductor

San Diego, California, United States -

Full Time

Start Date

Immediate

Expiry Date

19 May, 26

Salary

155000.0

Posted On

18 Feb, 26

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Mixed-Signal IC Verification, Verification Plan Development, Component Modelling, Test Bench Creation, AMS Simulation, Analog/Digital Interaction Verification, System Level IC Connectivity Verification, AMS Verification Methodology, Verilog-AMS Modelling, Functional Coverage, Code Coverage, Gate-Level Simulations, Power Verification, Formal Verification, SystemVerilog, UVM

Industry

Semiconductor Manufacturing

Description

At Elevate Semiconductor, our mission is to empower semiconductor and system test customers by delivering world-class test integrated circuits (ICs) that tackle the industry's most complex automated test equipment (ATE) challenges. We pride ourselves on exceeding expectations by designing the lowest power, highest density solutions to achieve the lowest possible cost of test both today and for the future. We are seeking an experienced Mixed-signal IC Verification Engineer, to join our IC development team developing high-performance analog and mixed-signal ICs. You will own the end-to-end verification lifecycle, from developing the verification plan, modelling components, creating test benches, and performing analog/mixed-signal (AMS) simulation of the design. This includes both verification of analog / digital interaction at the block level (e.g. feedback loops) and verification of system level IC connectivity. The ideal candidate will have worked closely with both analog and digital designers to verify mixed-signal IC designs prior to tape out and have a keen interest in developing and maintaining AMS verification methodology best practice. This is an excellent opportunity to make a measurable impact in a fast-paced environment where innovation, precision, and collaboration drive success. This role will require you to work onsite in San Diego, CA. Responsibilities Develop and execute verification test plans for mixed-signal ICs based on design specifications. Define and implement advanced simulation test benches (e.g. with randomized, rule based, stimulus) to verify functionality and performance. Produce Verilog-AMS models of analog circuits to accelerate verification process. Develop functional and code coverage models and drive coverage closure. Perform gate-level simulations, power verification, and formal verification as required. Collaborate closely with digital design and analog design teams to identify appropriate verification strategy, including corner case coverage. Support post-silicon validation/debug. Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in mixed-signal IC design verification. Solid understanding of mixed-signal IC verification methodologies and flows. Expertise in test bench design and behavioral modelling. Proficiency in functional and code coverage methodologies. Expertise in SystemVerilog, UVM, and Verilog. Experience with Verilog AMS and AMS simulation environments (e.g. Spectre AMS Designer). Excellent communication and team working skills. 100% Employer Paid Health Insurance (Medical, Dental, Vision) Unlimited Paid Time Off Performance Bonuses Free Lunch Catered in by Local Restaurants Private Equity Options Retirement Plans Sabbatical Program Tuition Reimbursement Volunteer Days Relocation Assistance Conference Attendance Support Biweekly Phone Stipend Employee Assistance Program The salary range for this role is $114,000.00-$155,000.00. Starting salary will be aligned with your relevant experience and demonstrated capabilities during the interview process. Typically, candidates begin at the initial tier of our compensation range, with placement adjusted for candidates presenting extensive directly applicable experience.

Responsibilities

The engineer will own the end-to-end verification lifecycle, including developing verification plans, modeling components, creating test benches, and performing analog/mixed-signal simulation of the design. Key tasks involve developing and executing verification test plans, defining advanced simulation test benches, producing Verilog-AMS models, and driving coverage closure.