Mixed-Signal Model Verification Engineer at Apple

Cupertino, California, United States -

Full Time

Start Date

Immediate

Expiry Date

28 Jan, 26

Salary

0.0

Posted On

30 Oct, 25

Experience

2 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, Assertions, Circuit Schematics, Logic Simulations, SPICE Simulations, HDL Co-simulations, Digital Logic Gates, Clocking, State Elements, Passive Circuit Elements, Active Circuit Elements, Voltage Sources, Current Sources, Analog Blocks, PERL Scripting, Python Scripting

Industry

Computers and Electronics Manufacturing

Description

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and detail oriented Mixed-signal Behavioral Model Verification Engineer. If you are early in your journey towards a chip design career and wish to challenge yourself in a technical and multi-disciplinary effort, come join the Apple mixed-signal silicon design team. In this position you will build a strong foundation in the working of full custom analog and high-speed digital circuits. You will work with experts in circuit design, behavioral modeling and design verification. You will gain expertise in hybrid simulation methods and various flows used to verify full custom designs. DESCRIPTION In this job you will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. The verification process will involve creating self-checking testbenches to simulate models against the circuits they were derived from. It will also involve functional testing of the model against the specification and creating assertions to flag illegal operating conditions. You will additionally help setup and run various static flows like formal logical equivalence, linting, and timing checks. You will also contribute to the streamlining and automation of these flows across mixed-signal design teams. MINIMUM QUALIFICATIONS Bachelor’s degree with minimum 3 years of relevant experience PREFERRED QUALIFICATIONS Excellent knowledge of SystemVerilog and Assertions Ability to read custom circuit schematics and understand functionality Solid understanding of logic/SPICE simulations as well as SPICE/HDL co-simulations Excellent knowledge of digital logic gates, clocking and state elements Basics of passive and active circuit elements, voltage and current sources, and analog blocks like amplifiers ADCs/DACs/Comparators Familiarity of writing scripts in PERL/Python is a strong plus Familiarity with formal equivalence and Lint/CDC/RDC tools is a strong plus

Responsibilities

You will be responsible for verifying mixed-signal behavioral models written in SystemVerilog. This includes creating self-checking testbenches and functional testing of the model against specifications.