MTS Memory Sustaining Design Engineer, HBM at Micron Technology

Richardson, Texas, United States -

Full Time

Start Date

Immediate

Expiry Date

04 Jan, 26

Salary

0.0

Posted On

06 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

CMOS Circuit Design, Parasitic Modeling, Design Validation, Power Delivery Network Analysis, DRAM Operation, JEDEC Specifications, Schematic Entry, Digital Modeling, Analog Modeling, High-Speed Clocking, Interface Development, RTL Design Flow, Scripting Languages, 3D Packaging Technologies, Problem-Solving, Mentorship

Industry

Semiconductor Manufacturing

Description

Contribute to the design, layout, and optimization of Memory, Logic, and Analog circuits for HBM products. Parasitic modeling and assisting in design validation, reticle experiments, and required tape-out revisions. Collaborate with layout teams to meet floorplanning, placement, and routing requirements. Simulate and verify designs using industry-standard tools (e.g., FINESIM, HSPICE, Verilog). Perform extensive power delivery network analysis and optimization. Assist in running various design checks prior to initial tapeout and revision tapeout. Be proactive in identifying and flagging design issues, performance problems, and opportunities to improve design performance and reduce power consumption. Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products. Provide mentorship and support to team members. Review and check design specifications to ensure high quality. Engage with various teams like Product Engineering, Test, Probe, Process Integration, Packaging, Technology Development and Marketing to ensure performance & manufacturability, to support issues with current HBM designs and find opportunities to innovate on future HBM solutions. BS or MS in Electrical Engineering or a related equivalent field. Proven relevant experience of 12+ years with BS or 10+ years with MS. Extensive knowledge of CMOS circuit design and good understanding of semiconductor device physics. Experience with schematic entry, digital (Verilog) and analog (FastSpice & Hspice) modeling and simulations. Good understanding of timing/area/power/complexity trade-offs in DRAM or mixed-signal design. Extensive knowledge with DRAM operation and JEDEC specifications, preferably with the HBM product family. In depth technical expertise in one or more areas - memory array design, high-speed clocking and interface development, logic and custom circuit design, power delivery optimization, 3D packaging technologies. Good verbal and written communication skills with the ability to efficiently synthesize and convey sophisticated technical concepts to other team members and leadership. Experience with scripting languages (Python, TCL, Perl, etc.) Proven track record of innovation and problem-solving in high-performance memory development. Good experience with RTL Design flow, in DRAM process or Foundry process. Prior experience with package technologies (TSV, hybrid bonding, interposers, etc).

Responsibilities

Contribute to the design, layout, and optimization of Memory, Logic, and Analog circuits for HBM products. Collaborate with layout teams and engage with various teams to ensure performance and manufacturability of HBM designs.